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s3c72i9/p72i9 product overview 1- 1 1 product overview overview the s3c72i9 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 -bit cpu core, sam47 (samsung arrangeable microcontrollers). with an up-to-896-dot lcd direct drive capability, 8-bit timer/counter 0, 16-bit timer/counter 1 , and serial i/o, the s3c72i9 offers an excellent design solution for a wide variety of applications which require lcd func tions. up to 39 pins of the 100-pin qfp package can be dedicated to i/o. eight vectored interrupts provide fast response to internal and external events. in addi tion, the s3c72i9 's advanced cmos technology pro vides for low power consumption and a wide oper at ing voltage range. otp the s3c72i9 microcontroller is also available in otp (one time programmable) version, S3P72I9. S3P72I9 microcontroller has an on-chip 32 k-byte one-time-programable eprom instead of masked rom. the S3P72I9 is comparable to s3c72i9, both in function and in pin configuration.
product overview s3c72i9/p72i9 1- 2 features summary memory ? 8,192 4-bit ram (excluding lcd display ram) ? 32 , 768 8-bit rom 39 i/o pins ? i/o: 35 pins ? input only: 4 pins lcd controller/driver ? 56 segments and 16 common terminals ? 8 and 16 common selectable ? internal resistor circuit for lcd bias ? all dot can be switched on/off 8-bit basic timer ? 4 interval timer functions ? watchdog timer 8-bit timer/counter 0 ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider ? serial i/o interface clock generator 16-bit timer/counter 1 ? programmable 16-bit timer ? external event counter ? arbitrary clock frequency output ? ext ernal clock signal divider 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first or msb-first transmission selectable ? internal or external clock source memory-mapped i/o structure ? data memory bank 15 watch timer ? time interval generation: 0.5 s, 3.9 ms at 32 . 768 hz ? 4 frequency outputs to buz pin ? clock source generation for lcd interrupts ? four internal vectored interrupts ? four external vectored interrupts ? two quasi-interrupts bit sequential carrier ? suppor ts 16-bit serial data transfer in arbitrary format power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system clock and cpu clock stop ) ? sub-system clock stop mode oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 0.4 - 6 mhz ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.67, 1.33, 10.7 s at 6 mhz ? 0.95, 1.91, 15.3 s at 4.19 mhz ? 122 s at 32.768 khz operating temperature ? - 40 c to 85 c operating voltage range ? 1.8 v to 5.5 v (3.0 mhz @ 1.8 v) package type ? 100-pin qfp
s3c72i9/p72i9 product overview 1- 3 block diagram vlc1-vlc5 com0-com7 p4.0-p5.3/ com8-com15 seg0-seg39 p9.3-p6.0/ seg40-seg55 lcd driver/ controller program status word stack pointer arithmetic and logic unit instruction internal interrupts reset p8.0-p8.3 seg47-seg44 i/o port 8 i/o port 9 p9.0-p9.3 seg43-seg40 8-bit timer/ counter 0 interrupt control block instruction register clock 16-bit timer/ counter 1 32 k byte program memory 8192 x 4-bit data memory serial i/o i/o port 0 p0.0/ sck /ko p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 p6.0-p6.3 seg55-seg52 ks4-ks7 p7.0-p7.3 seg51-seg48 i/o port 7 i/o port 6 p5.0-p5.3/ com12-com15 p4.0-p4.3/ com8-com11 i/o port 5 i/o port 4 i/o port 3 p3.0/tclo0 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 i/o port 2 p2.0/clo p2.1/lcdck p2.2/lcdsy input port 1 p1.0-p1.3/ int0-int4 xt out x out xt in x in basic timer watch timer figure 1 -1 . s3c72i9 simplified block diagram
product overview s3c72i9/p72i9 1- 4 pin assignments seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 com0 com1 com2 com3 com4 com5 com6 com7 p4.0/com8 p4.1/com9 p4.2/com10 p4.3/com11 p5.0/com12 p5.1/com13 p5.2/com14 p5.3/com15 p6.0/seg55/k4 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 p9.3/seg40 p9.2/seg41 p9.1/seg42 p9.0/seg43 p8.3/seg44 p8.2/seg45 p8.1/seg46 p8.0/seg47 p7.3/seg48 p7.2/seg49 p7.1/seg50 p7.0/seg51 p6.3/seg52/k7 p6.2/seg53/k6 p6.1/seg54/k5 seg4 seg3 seg2 seg1 seg0 v lc5 v lc4 v lc3 v lc2 v lc1 p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 v dd v ss x out x in test xt in xt out reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/clo p2.1/lcdck p2.2/lcdsy p3.0/tclo0 s3c72i9 (100-qfp-1420c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 figure 1 -2 . s3c72i9 100-qfp pin assignment diagram
s3c72i9/p72i9 product overview 1- 5 pin descriptions table 1- 1 . s3c72i9 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test are possible. individual pins are software configurable as input or output. individual pins are software configurable as open- drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 11 12 13 14 sck /k0 so/k1 si/k2 buz/k3 p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test are possible. 4 -bit pull-up resistors are assignable by software . 23 24 25 26 int0 int1 int2 int4 p2.0 p2.1 p2.2 i/o same as port 0 except that port 2 is 3-bit i/o port. 27 28 29 clo lcdck lcdsy p3.0 p3.1 p3.2 p3.3 i/o same as port 0 . 30 31 32 33 tclo0 tclo1 tcl0 tcl1 p4.0 - p4.3 p5.0 - p5.3 i/o 4-bit i/o ports. 1-, 4-bit or 8-bit read/write and test are possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 42-45 46-49 com8 - com11 com12 - com15 p6.0 - p6.3 p7.0 - p7.3 i/o same as p4, p5. 50-53 54-57 seg55/k4 - seg52/k7 seg5 1- seg48 p8.0 - p8.3 p9.0 - p9.3 i/o same as p4, p5. 58-61 62-65 seg47 - seg44 seg43 - seg40 sck i/o serial i/o interface clock signal . 11 p0.0/k0 so i/o serial data output . 12 p0.1/k1 si i/o serial data input . 13 p0.2/k2 buz i/o 2 khz, 4 khz, 8 khz or 16 khz frequency output for buzzer signal. 14 p0.3/k3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. 23, 24 p1.0, p1.1
product overview s3c72i9/p72i9 1- 6 table 1- 1. s3c72i9 pin descriptions (continued) pin name pin type description number share pin int2 i quasi-interrupt with detection of rising or falling edges . 25 p1.2 int4 i external interrupt with detection of rising or falling edges . 26 p1.3 clo i/o clock output . 27 p2.0 lcdck i/o lcd clock output for display expansion . 28 p2.1 lcdsy i/o lcd synchronization clock output for display expansion . 29 p2.2 tclo0 i/o timer/counter 0 clock output . 30 p3.0 tclo1 i/o timer/counter 1 clock output . 31 p3.1 tcl0 i/o external clock input for timer/counter 0 . 32 p3.2 tcl1 i/o external clock input for timer/counter 1 . 33 p3.3 com0 - com7 o lcd common signal output . 34-41 ? com8 - com11 i/o 42 -45 p4.0 - p4.3 com12 - com15 46-49 p5.0 - p5.3 seg0 - seg39 o lcd segment signal output . 5-1, 100-66 ? seg40 - seg43 i/o 65-62 p9.3 - p9.0 seg44 - seg47 61-58 p8.3 - p8.0 seg48 - seg51 57-54 p7.3 - p7.0 seg52 - seg55 53-50 p6.3/k7 - p6.0/k4 k0 - k3 i/o external interrupt. the triggering edge is selectable. 11-14 p0.0 - p0.3 k4 - k7 50-53 p6.0 - p6.3 v dd ? main power supply . 15 ? v ss ? ground . 16 ? reset i reset signal . 22 ? v lc 1- v lc5 ? lcd power supply . 10-6 ? x in, x out ? crystal, c eramic or rc oscillator pins for system clock. 18, 17 ? xt in, xt out ? crystal oscillator pins for subsystem clock. 20, 21 ? test i test signal input . (must be connected to v ss ) 19 ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode.
s3c72i9/p72i9 product overview 1- 7 table 1- 2 . overview of s3c72i9 pin data pin names share pins i/o type reset value circuit type p0. 1, p0.3 so/k1, buz/k3 i/o input e-1 p0. 0, p0.2 sck /k0, si/k2 i/o input e-2 p1.0 - p1. 3 int0 - int2 , int4 i input a- 3 p2.0 - p2.2 clo, lcdck, lcdsy i/o input e p3.0 - p3.1 tclo0, tclo1 i/o input e p3.2 - p3.3 tcl0, tcl1 i/o input e-1 p4.0 - p4.3 p5.0 - p5.3 com8 - com11 com12 - com15 i/o input h-13 p6.0 - p6.3 seg55/k4 - seg52/k7 i/o input h-16 p7.0 - p7.3 seg5 1- seg48 i/o input h-13 p8.0 - p8.3 p9.0 - p9.3 seg47 - seg44 seg43 - seg40 i/o input h-13 com0 - com7 ? o high h-3 seg0 - seg39 ? o high h-15 v dd ? ? ? ? v ss ? ? ? ? reset ? i ? b v lc 1 - v lc5 ? ? ? ? x in , x out ? ? ? ? xt in , xt out ? ? ? ? test ? i ? ?
product overview s3c72i9/p72i9 1- 8 pin circuit diagrams p-channel n-channel in v dd figure 1 -3 . pin circuit type a schmitt trigger pull-up resistor v dd pull-up resistor enable in p-channel figure 1 -4 . pin circuit type a- 3 schmitt trigger in v dd pull-up resistor figure 1 -5 . pin circuit type b p-channel n-channel v dd out output disable data figure 1 -6 . pin circuit type c
s3c72i9/p72i9 product overview 1- 9 n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1 -7 . pin circuit type e schmitt trigger n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1 -8 . pin circuit type e-1
product overview s3c72i9/p72i9 1- 10 n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data schmitt trigger figure 1 -9 . pin circuit type e-2
s3c72i9/p72i9 product overview 1- 11 out v dd v lc1 com v lc5 v lc4 figure 1 -10 . pin circuit type h-3 out v dd v lc2 seg v lc5 v lc3 figure 1 - 1 1 . pin circuit type h-15
product overview s3c72i9/p72i9 1- 12 com/seg output disable type h-3 i/o data type c v dd p-ch pull-up resistor pull-up resistor enable figure 1 - 1 2 . pin circuit type h-13 seg output disable type h-15 i/o data schmitt trigger type c v dd p-ch pull-up resistor pull-up resistor enable figure 1 - 1 3 . pin circuit type h-16
s3c72i9/p72i9 electrical data 14 - 1 14 electrical data overview in this section, information on s3c72i9 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abs olute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c72i9/p72i9 14 - 2 table 14 - 1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? - 0.3 to + 6.5 v input voltage v i ports 0 - 9 - 0.3 to v dd + 0.3 v output voltage v o ? - 0.3 to v dd + 0.3 v output current high i oh one i/o p in active - 15 ma all i/o pins active - 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) total for ports 0, 2 - 9 + 100 (peak value) + 60 (note) operating temperature t a ? - 40 to + 85 c storage temperature t stg ? - 65 to + 150 c note : the values for output current low ( i ol ) are calculated as peak value duty . table 14 - 2 . d.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 - v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 6, p3.2, p3.3, and reset 0.8 v dd v dd v ih3 x in , x out , and xt in v dd - 0. 1 v dd input low voltage v il1 all input pins except those specified below for v il2 - v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 6, p3.2, p3.3, and reset 0.2 v dd v il3 x in , x out , and xt in 0. 1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = - 1 m a ports 0, 2 - 9 v dd - 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma p orts 0, 2 - 9 ? ? 2.0 v
s3c72i9/p72i9 electrical data 14 - 3 table 14 - 2 . d.c. electrical characteristics (continued) (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in , x out , xt in , and reset 20 input low leakage i lil1 v i = 0 v all input pins except those specified below for i lih2 ? ? - 3 a current i lil2 v i = 0 v x in , x out , and xt in - 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? - 3 a pull-up resistor r l i v i = 0 v; v dd = 5 v port 0 - 9 25 47 100 k w v dd = 3 v 50 95 200 r l 2 v i = 0 v; v dd = 5 v , reset 100 220 400 v dd = 3 v 200 450 800 lcd voltage dividing resistor r lcd t a = 25 c 25 55 80 k w | v dd -com i | voltage drop (i = 0 - 15) v dc - 15 a per common pin ? ? 120 mv | v dd -segx| voltage drop (x = 0 - 55) v ds - 15 a per segment pin ? ? 120 v lc1 output voltage v lc1 lcd clock = 0 hz, v lc5 = 0 v 0.8 v dd - 0.2 0.8 v dd 0.8 v dd + 0.2 v v lc2 output voltage v lc2 0.6 v dd - 0.2 0.6 v dd 0.6 v dd + 0.2 v lc3 output voltage v lc3 0.4 v dd - 0.2 0.4 v dd 0.4 v dd + 0.2 v lc4 output voltage v lc4 0.2 v dd - 0.2 0.2 v dd 0.2 v dd + 0.2
electrical data s3c72i9/p72i9 14 - 4 table 14 - 2 . d.c. electrical characteristics (concluded) (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 5.1 3.9 10.0 7.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 2.5 1.8 4.0 3.0 i dd2 ( 2 ) idle mode; v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 22.8 35 a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6.4 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b 2.5 5 stop mode; v dd = 3 v 10% xt = 0v 0.5 3 stop mode; v dd = 5 v 10% scmod = 0100b 0.2 3 stop mode; v dd = 3 v 10% 0.1 2 notes: 1. data includes power consumption for subsystem clock oscillation. 2 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 3. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents .
s3c72i9/p72i9 electrical data 14 - 5 table 14 - 3 . main system clock oscillator characteristics (t a = - 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range ; v dd = 3.0 v. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 3.0 v ? ? 10 ms v dd = 2. 0 v to 5 .5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh, t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency r = 2 0 k w , v dd = 5 v ? 2 ? mhz r = 39 k w , v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is ter minated.
electrical data s3c72i9/p72i9 14 - 6 table 14-4. recommended oscillator constants (t a = - 40 c + 85 c, v dd = 1.8 v to 5.5 v ) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz-6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz-6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz-6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38 pf built in.
s3c72i9/p72i9 electrical data 14 - 7 table 14 -5. subsystem clock oscillator characteristics (t a = - 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 2. 0 v to 5 .5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl, t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs. table 14 -6. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf
electrical data s3c72i9/p72i9 14 - 8 table 14 -7. a.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units instruction cycle time ( note ) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 2. 0 v to 5 .5 v 0.95 64 tcl0, tcl1 input frequency f ti0, f ti1 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 2. 0 v to 5 .5 v 1 tcl0, tcl1 input high, low width t tih0, t til0 t tih1, t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 2. 0 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v; input 800 ? ? ns internal sck source ; output 650 v dd = 2. 0 v to 5.5 v; input 3200 internal sck source ; output 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v; input 325 ? ? ns internal sck source ; output t kcy / 2- 50 v dd = 2. 0 v to 5 .5 v ; input 1600 internal sck source ; output t kcy / 2 - 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v ; input 100 ? ? ns v dd = 2.7 v to 5.5 v ; output 150 v dd = 2.0 v to 5.5 v ; input 150 v dd = 2.0 v to 5.5 v ; output 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v ; input 400 ? ? ns v dd = 2.7 v to 5.5 v ; output 400 v dd = 2.0 v to 5.5 v ; input 600 v dd = 2.0 v to 5.5 v ; output 500 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
s3c72i9/p72i9 electrical data 14 - 9 table 14 -7. a.c. electrical characteristics (continued) (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units output delay for sck to so t kso v dd = 2.7 v to 5.5 v ; input ? ? 300 ns v dd = 2.7 v to 5.5 v ; output 250 v dd = 2.0 v to 5.5 v ; input 1000 v dd = 2.0 v to 5.5 v ; output 1000 interrupt input high, low width t inth, t intl int0 , int1, int2, int4, k 0 - k7 10 ? ? s reset input low width t rsl input 10 ? ? s note: minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting. 1.5 mhz cpu clock 1.05 mhz 750 khz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v figure 14 - 1 . standard operating voltage range
electrical data s3c72i9/p72i9 14 - 10 table 14 -8. ram data retention supply voltage in stop mode (t a = - 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 /fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s3c72i9/p72i9 electrical data 14 - 11 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 14 - 2 . stop mode release timing when initiated b y reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 14 - 3 . stop mode release timing when initiated b y interrupt request
electrical data s3c72i9/p72i9 14 - 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14 - 4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14 - 5 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 14 - 6 . clock timing measurement at xt in
s3c72i9/p72i9 electrical data 14 - 13 tcl0 t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 14 - 7 . tcl timing reset t rsl 0.2 v dd figure 14 - 8 . input timing for reset reset signal int0, 1, 2, 4, k0 to k7 t inth t intl 0.8 v dd 0.2 v dd figure 14 - 9 . input timing for external interrupts and quasi-interrupts
electrical data s3c72i9/p72i9 14 - 14 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 14 - 10 . serial data transfer timing
s3c72i9/p72i9 michani cal data 1 5- 1 1 5 michanical data overview the s3c72i9 microcontrollers are available in a 100-qfp-1420c package. note : dimensions are in millimeters. 100-qfp-1420c #100 #1 20.00 0.2 14.00 0.2 17.90 0.3 23.90 0.3 0.10 max 0.65 (0.83) 0.10 max (0.58) 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.15 +0.10 -0.05 0-8 0.3 0.1 0.80 0.20 figure 15-1. 100-qfp package dimension
s3c72i9/p72i9 s3p72 i9 otp 16- 1 16 S3P72I9 otp overview the S3P72I9 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c72i9 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P72I9 is fully compatible with the s3c72i9, both in function and in pin configuration. because of its simple programming requirements, the S3P72I9 is ideal for use as an evaluation chip for the s3c72i9.
S3P72I9 otp s3c72i9/p72i9 16- 2 seg4 seg3 seg2 seg1 seg0 v lc5 v lc4 v lc3 v lc2 v lc1 p0.0/ sck /k0 p0.1/so/k1 sdat /p0.2/si/k2 sclk /p0.3/buz/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/clo p2.1/lcdck p2.2/lcdsy p3.0/tclo0 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 com0 com1 com2 com3 com4 com5 com6 com7 p4.0/com8 p4.1/com9 p4.2/com10 p4.3/com11 p5.0/com12 p5.1/com13 p5.2/com14 p5.3/com15 p6.0/seg55/k4 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 p9.3/seg40 p9.2/seg41 p9.1/seg42 p9.0/seg43 p8.3/seg44 p8.2/seg45 p8.1/seg46 p8.0/seg47 p7.3/seg48 p7.2/seg49 p7.1/seg50 p7.0/seg51 p6.3/seg52/k7 p6.2/seg53/k6 p6.1/seg54/k5 S3P72I9 (100-qfp-1420c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 note: the bolds indicate an otp pin name. figure 16-1. S3P72I9 pin assignments (100-qfp package)
s3c72i9/p72i9 s3p72 i9 otp 16- 3 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.2 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p0.3 sclk 14 i/o serial clock pin. input only pin. test v pp (test) 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 22 i chip initialization v dd /v ss v dd /v ss 15/16 i logic power supply pin. v dd should be tied to + 5 v during programming. table 16-2. comparison of S3P72I9 and s3c72i9 features characteristic S3P72I9 s3c72i9 program memory 32 kbyte eprom 32 kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P72I9, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P72I9 otp s3c72i9/p72i9 16- 4 table 1 6-4. d.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 5.1 3.9 10.0 7.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 2.5 1.8 4.0 3.0 i dd2 ( 2 ) idle mode; v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 22.8 35 a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6.4 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b 2.5 5 stop mode; v dd = 3 v 10% xt = 0v 0.5 3 stop mode; v dd = 5 v 10% scmod = 0100b 0.2 3 stop mode; v dd = 3 v 10% 0.1 2 notes: 1. data includes power consumption for subsystem clock oscillation. 2 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 3. currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output po rt drive currents .
s3c72i9/p72i9 s3p72 i9 otp 16- 5 1.5 mhz cpu clock 1.05 mhz 750 khz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 1.8 v figure 1 6-2. standard operating voltage range

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